The present disclosure is related generally to the field of electronics, and more specifically but not exclusively, to compensating for an excess capacitance in a circuit board or package.
It is commonly recognized that multi-gigabit per second platform communication channels may be performance limited due to various effects related to the overall transmission line quality of the channel's physical implementation (i.e., printed circuit board (PCB) and package wiring, connectors, chip sockets, etc.). Notably important are factors such as conductor and dielectric losses, impedance mismatch and stub effects. Methods to handle via stubs and the large capacitance they may create have concentrated on their removal or avoidance, namely, by PCB via back drilling or the use of sequential lamination PCB processes that produce blind or buried vias. Both of these approaches, however, are costly to implement.